In general, semiconductor memory devices are becoming increasingly highly-integrated and operating at increasingly higher clock speeds. In order to accomplish this, it may be desirable to substantially reduce power consumption and/or signal noise in the memory device. In particular, in a data “read” operation, it may be desirable for such devices to operate with low power consumption and/or low signal noise.
FIG. 1 is a block diagram illustrating a data read path in a conventional semiconductor memory device. Referring to FIG. 1, a data read path includes a memory cell 10, a bit line sense amplifier 20, an input/output sense amplifier 30, a data output buffer circuit 40 and a pad 50. The data output buffer circuit 40 may include a data output driver circuit.
In a data read operation, data stored in a memory cell 10 is provided on a bit line, where it is sensed and amplified in a bit line sense amplifier 20. The data is amplified in an input/output sense amplifier 30 through a global line, e.g., a global bit line and/or a global input/output line. Data amplified in the input/output sense amplifier 30 is converted into a signal having the appropriate configuration of bits. The data is output to the pad 50 through the output buffer circuit 40. Thus, the data stored in the memory cell 10 is output through several circuits, each of which may impart noise to the signal and/or may consume electric power.
In the circuits forming the read path of a semiconductor memory device, and in particular when data read from a memory cell is output to an external circuit through a data output buffer circuit, signal noise and/or power consumption may be relatively large. That is, it is known that the signal noise and/or power consumption may be relatively large in a data output buffer circuit including an output driver circuit.
For this reason, a transistor used as an output terminal, e.g., an output driver circuit, of the data output buffer circuit may have a considerably large channel width relative to other components of the chip, so as to provide impedance isolation between the chip exterior and interior, and/or to facilitate high speed data access. When the transistor constituting an output terminal of a data output buffer performs a given output operation, such as a swing operation that is performed from a ‘high’ level to a “low” level or from a “low” level to a “high” level, a large current may flow momentarily, which may be a source of additional signal noise.
As one solution for this problem, the concept of a data bus inversion (DBI) device or circuit was introduced. A data bus inversion circuit may be useful for providing reliable, high-speed data transmission between chips.
FIG. 2 is a block diagram of a conventional data bus inversion circuit. As shown in FIG. 2, a data bus inversion (DBI) circuit 80 may be provided within a semiconductor memory device ahead of a data output buffer circuit, so as to reduce power consumption and/or signal noise in the data output buffer circuit. The data bus inversion circuit 80 inverts, or does not invert, and outputs an input data signal Din. An inverted, or non-inverted, output data signal Dout output from the data bus inversion circuit 80 is provided to the outside through a data output buffer circuit.
An example of a data bus inversion circuit is disclosed in United States Pre-grant Publication No. 2004/0068594.
Such a data bus inversion circuit was known merely conceptually to those skilled in the art, and concrete technical realizations or exemplary embodiments were not well known. Thus, there may be problems in realizing semiconductor memory devices from the viewpoint of putting them to practical use for reducing power consumption and/or signal noise.